EPROMs and Flash E.sup.2 PROMs (hereafter collectively, PROMs) have several structures which allow them to hold a charge without refresh for extended periods of time (see FIG. 1). The charge itself is stored on a "floating gate" 10 also referred to as Poly 1 or P1, which is a structure of polycrystalline silicon (hereafter, poly) surrounded on all sides by a layer of oxide 12. Located superjacent and parallel to this P1 structure is another poly structure, the word line or "control gate" 14 or P2. P1 10 and P2 14 act as the two plates of a capacitor. Below the P1 layer are two N+ junctions, one which acts as the transistor source 16 and the other as the drain 18, which are doped into a p-type substrate 20. The portion of the substrate 20 between the source 16 and the drain 18 is the channel 22. The cell of FIG. 1 functions like an enhancement-type n-channel metal oxide semiconductor field effect transistor (MOSFET) with two gates of poly.
There are many ways to program a flash E.sup.2 PROM. For example, a potential such as 8 V is applied between source and drain. Simultaneously, a large voltage pulse, for example 12 V, is applied to the control gate. The large positive voltage on the control gate establishes an electric field in the insulating oxide. This electric field attracts the electrons generated from the so-called avalanche breakdown of the transistor due to the high drain and control gate voltages, and accelerates them toward the floating gate, which they enter through the oxide. In this way the floating gate is charged, and the charge that accumulates on it becomes trapped.
To return the floating gate from a charged state to a state with no charge, the charge is returned to the substrate. In an EPROM, this is accomplished with ultraviolet light which excites the electrons on the floating gate past a certain energy state, thereby allowing them to pass through the oxide and return to the substrate. In an E.sup.2 PROM, this excitation is accomplished with an electrical field.
The voltage which must be applied on the control gate to turn on the transistor is much higher in a device storing a charge than in a device which does not have a voltage potential stored on P1. To read the content of the floating gate, a voltage somewhere between the low and high voltage values (i.e. the threshold voltage V.sub.t) is applied to the control gate. A cell that trips at V.sub.t has no charge stored on P1, while a cell which does not trip is determined to be storing a charge.
There are structures which make up a PROM array which are common to several transistors in the array. FIG. 2 shows a top view of an array showing transistor sources 16, drains 18, digit lines 24, floating gates 10, and control lines 26 which form control gates 14 as they pass over the floating gates 10. Also shown as a dotted line is the "active area" 28 interspersed with areas of field oxide 30. As shown in FIG. 2, a single control line 26 is common to all transistors in a single column, and when selected it activates all transistors in the column. The source regions 16, which run parallel with the control lines 26, are common to all transistors in two adjacent columns, although all source regions are the same point electrically across all transistors in the array or in a portion of the array. Individual transistor drains 18 are common to two transistors in adjacent columns. The digit (or bit) lines 24 are common with the drains 18 of all transistors in a single row.
To read the datum on a floating gate 10, the control line 26 of the cell to be read is activated which causes all transistors in the selected column to become active and to output the cell information on their respective digit lines 24. The information on the digit line 24 which corresponds to the cell to be read is obtained with a sense amplifier (not shown), with one sense amp for each digit line.
The "active area" 28 is defined during the manufacturing process after the thin pad oxide is initially formed on the surface of the wafer. After the pad oxide is formed on the surface of the wafer, a patterned layer of nitride is formed and the exposed oxide is caused to thicken. The nitride prevents the growth of the oxide underneath it, while allowing the exposed oxide to grow. The area under the nitride which remains thin is referred to as the gate oxide and is also called the active area. The exposed oxide which thickens becomes the field oxide. During an oxide etch, the gate oxide will erode away to bare silicon, as it is thinner than the field oxide. The bare areas can then be doped, with the field oxide protecting the other silicon areas from being doped.
FIG. 2 shows a conventional correctly-aligned PROM array. After the transistor control lines 26 and floating gates 10 and spacers (not shown) are formed, the surface of the wafer is doped so as to define the transistor sources 16 and the drains 18. "W" shows the minimum width of the source line which is formed during the doping. The width is determined by the width of the active area 28 which is doped, and is defined on the two outer edges by the field oxide which cannot be doped through, and on the two inner edges by the spacer oxide (not shown) covering the word lines 26.
There are various problems associated with the manufacture of present designs of PROMs, not the least of which is misalignment of surface structures with respect to the active area. For example, the control gates 26 can be misaligned so that they cover some of the active area 28 as shown in FIG. 3. The active area 28 covered by the misaligned control gate poly 26 is designated by a "P." This control gate poly 26 which covers the gate oxide P protects the gate oxide in this region from being etched away and the substrate below it from being doped. In this misaligned configuration, the doped area which makes up the source lines are greatly narrowed, and are indicated by W' in FIG. 3. If the control gates 26 are misaligned in this way, the floating gates 14 are also misaligned since the structures are formed by the same etch, thereby resulting in unfavorable changes to the electrical characteristics of the device. Conductivity along the source lines 28 decreases due to the increased resistivity which results from the narrowed lines. Also, there is a greater chance of interference between the digit lines 24 from the reduced conductivity path between drains 18 in adjacent rows.
There are currently two primary methods used to manufacture Flash E.sup.2 PROM and EPROM memory. A first manufacturing process is shown in FIGS. 4-8.
To get to the structure of FIG. 1, a first blanket layer of oxide, the pad oxide, is formed on top of the silicon substrate. Nitride is patterned in a crisscross pattern on the oxide to define the active area 28 as shown in FIG. 4, and the field oxide 30 is formed from the exposed pad oxide while the unexposed pad oxide becomes the gate oxide 28. As shown in FIGS. 5A and 5B, a first blanket layer of poly 50 which will make up P1 is formed on the appropriate areas of the gate oxide 28, and a second layer of oxide 52 and a layer of nitride 54, which separate P1 from a second poly layer is formed on the first poly layer 50. The P1 layer is patterned with a layer of resist 56 in rows, perpendicular to the source lines of the active area. As shown in FIG. 6, after a P1 sidewall oxidation (not shown) a second blanket poly layer 60, P2, is formed on the nitride layer 54, and an optional oxide layer 62 is formed on the Poly 2 60 layer, and photoresist 64 is patterned on the surface in columns perpendicular to the rows of P1 50. An etch forms the floating gates 10 and control gates 14. Referring to FIG. 7, a third blanket layer of oxide 70 is formed and etched, which forms the spacers 80 as shown in FIG. 8. During the spacer etch, exposed gate oxide 28 is also removed, thereby exposing the areas of silicon which will later become the transistor diffusion areas.
After the structure of FIG. 8 is formed, the substrate 20 is doped to form the N+areas of the transistor sources 16 and drains 18, and conductive areas which couple the sources between the rows. Next, a blanket layer of oxide is formed over the wafer surface, and a patterned layer of resist defines the digit line contacts to the drain regions. An etch is performed down to the substrate which removes any exposed material and defines the contacts. Finally, the resist is removed and a layer of metal is deposited.
With this process, misalignment can occur when the photoresist 64 is deposited which defines the control gates 14. If the mask used to pattern the photoresist 64 is misaligned, the structure of FIG. 3 might be produced, which has the problems of high resistivity which were described above. Misalignment can also occur during the formation of the photoresist which defines the digit lines. If the mask is misaligned, the destructive etch can expose the floating gate which would then make contact with the digit line, thereby producing an unusable wafer of devices. For this reason, the gates are usually more widely spaced to allow for more room in the drain areas, thereby allowing for some misalignment of the digit line contact mask. Allowing for more room, however, decreases the number of transistors that can be produced in a given area.
A second method of forming the Flash E.sup.2 PROM structure is described in the article "A 5-Volt Contactless Array 256 KBIT Flash EEPROM Technology," M. Gill et al, IEDM, 1988, pp. 428. This structure, which is formed with a buried N+ line process, has higher digit line capacitance, more process complexity, and also has a high degree of lateral diffusion in the buried digit line and is not easily scalable.